1. Field of the Invention
The invention relates to a multiple stacked-chip packaging structure and, more particularly, to a multiple stacked-chip packaging structure that is not subject to the layout patterns of bonding pads on the chip and is capable of protecting the lower chip and wires.
2. Description of the Related Art
As shown from FIG. 1A to FIG. 1C, the layout patterns of bonding pads 12, 16 & 20 on chips 10, 14 & 18 respectively are generally divided into three categories: peripheral type, middle type, and mixed type. When the wire bonding of multiple stacked-chip packaging is performed, it is quite impossible to place the middle type or mixed type chip on the lower layer with the conventional wire bonding technique because the upper layer chip will result in wire damage on the lower layer chip. Or, worse still, an open or short circuit of the wire can be resulted in, which eventually will fail the whole packaging body.
There have been many solutions proposed to solve the problem caused by protecting wire bonding on the lower structure of middle type or mixed type chip. As shown in FIG. 2, a middle-type chip 32 is located on a substrate 30 that has a groove in the middle of it, and a bonding pad (not shown) is located inside the groove facing downwards. In addition, a plurality of wires 34 are electrically connected to the bonding pads on the middle-type chip 32 and to the substrate 30, whereas another chip 36 is located on the middle-type chip 32, and a plurality of wires 38 are electrically connected to the bonding pads on the chip 36 and to the substrate 30. Finally, a molding compound 40 is used to seal up all the components. However, when the above method is in practice, a problem may occur; that is, a technique that is able to perform wire bonding at one side and not to impair wires at the other side is required during the operation. Unfortunately, the conventional processing technique is hard to achieve the required technique. Therefore, the method is problematic in real practice.
Next, another solution is to employ a nonconductive adhesive layer with strong adhesive to cover the wires of lower layer chip, and a height that is taller than the height of nonconductive adhesive layer of the wires on the lower layer chip has to be maintained. Also, as shown in FIG. 3, a lower layer chip 44 is located on the substrate 42, and a plurality of wires 46 are connected to the bonding pads (not shown) and to the substrate 42. Then, a nonconductive adhesive layer 48 is used to cover the lower layer chip 44 and the wires 46. After that, an upper layer chip 50 is provided on the nonconductive adhesive layer 48, and a plurality of wires 52 are electrically connected to the bonding pads (not shown) of the upper layer chip 50 and to the substrate 42. Finally, a molding compound 54 is used to seal up all the components. However, the degree of coplanar of a thicker nonconductive adhesive layer 48 is not easy to be controlled. Therefore, the wire bonding process of the upper layer chip 50 will be difficult. Consequently, the nonconductive adhesive layer 48 has to rely on the elements of the filler to maintain its own thickness. Yet, another problem may follow; that is, the lower layer wires may be impaired and therefore an open or short circuit problem may be resulted in since the nonconductive adhesive layer 48 will be softened and flattened during a subsequent high-temperature processing such as a reflow. Therefore, the method is not easy to be implemented, either.
In viewing the above-mentioned problems, the invention provides a multiple stacked-chip packaging structure to cope with the conventional shortcomings.